Optimization of power in different circuits using MTCMOS technique
- G.Raghu Nandan Reddy
- T.V. Ananthalakshmi
Power Gating, 5T D-flip flop, Schmitt trigger, Cadence tool
This paper enumerates low power, high speed designed circuits like 5T TSPC D-Flip Flop and 4T Schmitt trigger having less number of transistors. As the transistors used have small area and low power consumption, they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors, etc. So the leakage current of these devices will increase significantly with the shrinking of semiconductor process technologies. The most straight forward and effective method for reducing standby leakage is power-gating. In this Multithreshold Voltage Based CMOS (MTCMOS) technique is used as a power gating method to optimize power and delay in the circuits.
G.Raghu Nandan Reddy, T.V. Ananthalakshmi. "Optimization of power in different circuits using MTCMOS technique".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.2, Issue 2, pp.1573-1582, URL :https://rjwave.org/ijedr/papers/IJEDR1402048.pdf
Volume 2 Issue 2
Pages. 1573-1582
