Paper Title

Area-Efficient 128-bit Carry Select Adder Architecture

Authors

  • Srinivasareddy B
  • D.Manjularani

Keywords

Application specific integrated circuit (ASIC), area-efficient,CSLA, low power

Abstract

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed design in terms of area, power. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Article Type

Published

How To Cite

Srinivasareddy B, D.Manjularani. "Area-Efficient 128-bit Carry Select Adder Architecture".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.2, Issue 1, pp.210-214, URL :https://rjwave.org/ijedr/papers/IJEDR1401037.pdf

Issue

Volume 2 Issue 1 

Pages. 210-214

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