Paper Title

Impact of NBTI on SRAM Arrays for efficiency Improvement Through Recovery Boosting

Authors

  • A. Lavanya
  • P. Rama Krishna

Keywords

NBTI, SRAM, Recovery Boosting.

Abstract

Negative Bias Temperature Instability is an important lifetime reliability problem in microprocessors. SRAM based structures with in the processor are especially susceptible to NBTI since one of the pMOS devices in the cell always has an input of �0�. SRAM�s are widely used in controller & Processor memories. It supports high speed implementation. The SRAM exhibit a major problem called negative bias temperature instability (NBTI) while storing the data �0� so large amount of energy is wasted here. In our paper we are going to remove this hazard and we are going to modify the SRAM circuit using Recovery Boosting. As well as we are designing 4-Bit SRAM Through Recovery Boosting for improving READ and WRITE ability of the SRAM circuit. By this we are improving the efficiency of the circuit by reduction in power consumption. In this paper design, simulation, layout design are done by using DSCH and MICROWIND tools.

Article Type

Published

How To Cite

A. Lavanya, P. Rama Krishna. "Impact of NBTI on SRAM Arrays for efficiency Improvement Through Recovery Boosting".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.2, Issue 1, pp.14-18, URL :https://rjwave.org/ijedr/papers/IJEDR1401004.pdf

Issue

Volume 2 Issue 1 

Pages. 14-18

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