FPGA Implementation Of Five Port Network Router
- C.SUNIL
- SHAIK KHADAR SHARIF
- PRAVEEN VANAPARTHY
Network-on-Chip, Simulation Router, FIFO, FSM, Register blocks, Verilog-HDL, FPGA.
Multiprocessor system on chip is emerging as a new trend for System on chip design but the wire and power design constraints are forcing adoption of new design methodologies. Researchers pursued a scalable solution to this problem i.e. Network on Chip (NOC). Network on chip architecture better supports the integration of SOC consists of on chip packet switched network. Here we develop a Router is a packet based protocol. In this Router which taken functionality reference from actual Router the design is implemented on single chip using verilog code. Router drives the incoming packet which comes from the input port to output ports based on the address contained in the packet. The router has a one input port from which the packet enters. It has three output ports where the packet is driven out. The router has an active low synchronous input resetn which resets the router. Thus the idea is borrowed from large scale multiprocessors and wide area network domain and envisions on chip routers based network. This helps to understand how router is controlling the signals from source to destination based on the header adders. It also tells when data have to be extracted for a particular port and also it gives idea about port is full or empty. This method removes most of the problems cited above and improves the performance of router. The most familiar type of routers are home and small office routers that simply pass data, such as web pages and email, between the home computers and the owners‟ cable or DSL modem, which connects to the internet (ISP). Routers may also be used to connect two or more logical groups of computer devices known as subnets, each with a different sub-network address.
C.SUNIL, SHAIK KHADAR SHARIF, PRAVEEN VANAPARTHY. "FPGA Implementation Of Five Port Network Router".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.1, Issue 3, pp.0, URL :https://rjwave.org/ijedr/papers/IJEDR1303061.pdf
Volume 1 Issue 3
Pages. 0
