Paper Title

12 Bit Prefetch DDR3 & Speed Enhancement in DDR3 SDRAM using FIFO Synchronization Technique

Authors

  • Ankita Shrivastava
  • Sudha Nair

Keywords

Double Data Rate(DDR), First-In First-Out (FIFO), Field Programmable Gate Array(FPGA), Finite State Machine(FSM), Input-Output(I/O), Integrated Software Environment(ISE), Static Dynamic Random Access Memory(SDRAM), Look-Up-Table(LUT), Random Access Memory(RAM).

Abstract

The demand for high speed and small size memories has been increasing by the day. All device size is decreasing day-by-day in electronics industry for the best handing and carrying. Hence, these memory devices are rapidly developing to give high density and high memory bandwidths. However, with the increase in technology, complexity of instructions to control the memory devices also increases. This paper presents the technique and architecture of the DDR3 Controller which can be used to enhance the speed and discuss advantages of DDR3.

Article Type

Published

How To Cite

Ankita Shrivastava, Sudha Nair. "12 Bit Prefetch DDR3 & Speed Enhancement in DDR3 SDRAM using FIFO Synchronization Technique".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.4, Issue 3, pp.635-638, URL :https://rjwave.org/ijedr/papers/IJEDR1603104.pdf

Issue

Volume 4 Issue 3 

Pages. 635-638

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