Paper Title

Low Power High Speed Dynamic Latched Comparator

Authors

  • Sakshi Parolia
  • Shalini Singh

Keywords

Dynamic comparator. Latched comparator. Voltage sense amplifier (SA). Low-offset low-power high-speed

Abstract

Two dynamic latched comparators with DC offset voltage compensation are presented. In this paper, the dynamic latched comparators demonstrates lower offset voltage and higher load drivability, with two different techniques one is on transistor resistance and other is on source degeneration. In these techniques different transistors are added to the input source, by which DC offset voltage and energy is improved. The proposed comparators are designed using 90 nm PTM technology and 1 V power supply voltage in cadence orCAD capture tool. It demonstrates less offset voltage and less sensitivity of delay to decreasing input voltage difference than the conventional double-tail latched type voltage sense amplifier at approximately the same area and power consumption.

Article Type

Published

How To Cite

Sakshi Parolia, Shalini Singh. "Low Power High Speed Dynamic Latched Comparator".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.3, Issue 2, pp.778-780, URL :https://rjwave.org/ijedr/papers/IJEDR1502139.pdf

Issue

Volume 3 Issue 2 

Pages. 778-780

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