Design and Implementation of 16 bit Floating Point Processor for FFT applications
Butterfly; Field Programmable Gate Array (FPGA); Verilog HDL; 1024-point FFT
Floating point is considered to be an important format in which data is represented in fraction values. Floating Point calculation can be a daunting task for any processor because of the amount of resources and memory it takes for calculation. In this paper, we have presented and implemented a floating point architecture for application in FFT.
Deepak Dave, Aarti Bakshi. "Design and Implementation of 16 bit Floating Point Processor for FFT applications".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.3, Issue 1, pp.59-64, URL :https://rjwave.org/ijedr/papers/IJEDR1501013.pdf
Volume 3 Issue 1
Pages. 59-64