Efficient VLSI Architecture for Xilinx Vertex E based FFT & IFFT Structure

• Mamta Raj
• Prof.Sanket Choudhary
• Dr.Soni Changlani

FFT, Ripple Carry Adder, Carry Select Adder, Vedic Multiplier

Implementation of digital signal processing (DSP) algorithms in hardware, such as field VLSI, requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and image DSP applications. A high speed fast fourier transform (FFT) and IFFT design by using 8-bit, 16-bit 32-bit and 64-bit algorithm is presented in this paper. My work focus is on two key ideas for improving FFT and IFFT algorithm performance: (1) develop new high performance efficient complex multiplier structure. (2) Parallel processing used in this design. In all algorithms are implemented Xilinx vertex 2 device family and simulated Modalism.

Published

 Vol. 2 Issue. 4 Pages. 3855-3860

Mamta Raj, Prof.Sanket Choudhary, Dr.Soni Changlani. "Efficient VLSI Architecture for Xilinx Vertex E based FFT & IFFT Structure".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.2, Issue 4, pp.3855-3860, URL :https://rjwave.org/ijedr/papers/IJEDR1404075.pdf

Volume 2 Issue 4 

Pages. 3855-3860

Published Paper PDF : https://rjwave.org/ijedr/papers/IJEDR1404075.pdf

Published Paper URL : https://openrgate.org/viewfulldetails.php?id=1244

This work is licensed under a Creative Commons Attribution 4.0 International License and The Open Definition