Low Transistor Count Scalable Digital Comparator
- CH.Madhav
- Shafee Unnisa Syed
Comparator, Digital, Combinatorial logic, Gate Diffusion Input Cells, area
Comparator is the most frequent operation in many digital and scientific applications. Here in this paper we are simulating a low transistor count scalable digital comparator based on parallel prefix tree. Fastest comparators are designed by using the combinatorial logic gates, which results huge number of transistor count, and hence the area is also increased. So here we implemented the comparator using Gate Diffusion Input Cells to reduce the transistor count and hence the area of the circuit.
CH.Madhav, Shafee Unnisa Syed. "Low Transistor Count Scalable Digital Comparator".INTERNATIONAL JOURNAL OF ENGINEERING DEVELOPMENT AND RESEARCH ISSN:2321-9939, Vol.2, Issue 4, pp.3713-3717, URL :https://rjwave.org/ijedr/papers/IJEDR1404054.pdf
Volume 2 Issue 4
Pages. 3713-3717
